HYBRID MEMORY CUBE WILL KILL DDR TECHNOLOGY

The hybrid memory cube Consortium, which consists of such silicon luminaries as Micron, Samsung, and IBM, has finally finished hammering out the Hybrid Memory Cube 1.0 standard. The HMC is complete paradigm shift away from conventional DDR sticks that we all know pretty well. The new hybrid memory cube is 15 times faster than DDR3 while using 70% less energy. HMC 1.0 has max bandwidth of 320 GB/sec to a nearby CPU or GPU while standard DDR3 SDARM has on the other hand maxes out at just 24GB/sec.

Architecture of Hybrid Memory Cube

The Hybrid Memory Cube is essentially a stack of up to eight memory dies which are connected to each other through-silicon-via (TSVs), sitting atop a logic and switching layer that controls input and output to all eight dies. The stacked approach is fundamentally different from DRAM, which generally consists of a bunch of RAM dies placed side-by side on a stick. Almost all of HMC’s advantages over DRAM are due to the dies being stacked.

As you can see from the previous picture between laminate substrate there is lower density BGA ball count that connects memory die to landing pads on the top of the bottom package. Memory die typically require less I/O then the logic die. By putting dies on top of each other, the wires between them are much, much shorter. In turn, this means that data can be sent at higher speed, while at the same time using less energy. There are a few different chip stacking methods, though, with some being far more advanced and powerful than others. The most basic is package on package, which essentially takes two finished chips and places them on top of each other, with the connecting pins of the top ship fitting into the bottom chip.

The more advanced method of chip stacking uses through-silicon-vias (TSVs). With TSV, vertical copper channels are built into each memory die, so that when can be stacked on top of each other (pictured right). Unlike package-on-package, which sees two complete chips placed on top of each other, dies connected with TSV are all inside the same chip. This means the wires between the dies are as short as they can possibly be, and because each die is very thin, the complete package is only fractionally taller than normal. In theory, any number of dies can be connected this way, with heat generation and dissipation being the only real limitations. For now, it seems like the HMC 1.0 spec allows for up to eight dies, with a max addressable capacity of 8GB. There’s no reason you couldn’t multiple HMCs connected to a CPU or GPU, though, if you’re looking for more than 8GB of RAM.

Beyond TSV, the other reason that the HMC is so much faster and more efficient is because it removes the logic transistors form each DRAM die and places them all in one central location, at the base of the stack. In conventional DRAM, each and every memory chip has its own logic circuitry, which is in charge of getting data in and out of the individual memory cells. Beyond the TSV, the other reason that the HMC is so much faster and more efficient is because it removes the logic transistors from each DRAM die and places them all in one central location, at the base of the stack. In conventional DRAM, each and every memory chip has its own logic circuitry, which is in charge of getting data in and out of the individual memory cells. Each of these logic circuits needs to be powerful enough to read and write at huge data rates, which costs a lot of power and adds a lot of complexity to the I/O process. In the HMC, there is just one logic circuit that drives all eight memory dies. This centralized logic allows for higher and more efficient data rates — up to 320 gigabytes per second, while consuming 70% less energy than DDR3. The HMC Consortium consists of most major players in the chip industry, with the notable exception of Intel. Intel did collaborate with Micron when the Hybrid Memory Cube was first demonstrated at IDF in 2011, but for unknown reasons there are no TSV products on its roadmap. The consortium plans to launch the first HMCs later in 2013, and it is already working on version 2.0 of the HMC spec. There’s no word on cost, but we’ll probably see HMCs in supercomputers and networking devices first, where the ultra-high bandwidth will really come into its own, and then perhaps consumer devices in the next year or two.